
module sn76489_clock_div(
  input  wire clock_i,
  input  wire clock_en_i,
  input  wire res_n_i,
  output reg  clk_en_o  
);

reg [3:0] cnt_q;
reg [3:0] cnt_s;

always @(posedge clock_i or negedge res_n_i)begin
    if(!res_n_i)
	cnt_q <= #1 4'b0;
    else  
	cnt_q <= #1 cnt_s;
end

always @(*)begin
    if(clock_en_i)
	 if(cnt_q == 4'b0)begin
	     clk_en_o = 1'b1;
	     cnt_s    = 4'hf;
	 end
	 else begin
             clk_en_o = 1'b0;
	     cnt_s    = cnt_q - 1'b1;
	 end
    else begin
	clk_en_o = 1'b0;
	cnt_s    = cnt_q;
    end
end

endmodule
